3
Driver Electronic – PCB Drivers
1
8-08-2006
© by SEMIKRON
SEMIDRIVER
TM
SKHI 10
SEMIDRIVER
TM
SKHI 10/17
High Power Single IGBT Driver
General
The inligent single IGBT driver, SKHI10 respecti
vely
SKHI 10/17 is a standard driver for all power IGBTs
on
the market.
The high power output capability was designed to sw
itch
high current modules or several paralleled IGBTs ev
en for
high frequency applications. The output buffer has
been
improved to make it possible to switch up to 400A I
GBT
modules at frequencies up to 20kHz.
A new function has been added to the short circuit
protection circuitry （Soft Turn Off）, this automati
cally
increases the IGBT turn off time and hence reduces
the
DC voltage overvoltage spikes, enabling the use of
higher
DC-bus voltages. This means an increase in the fina
l
output power. An integrated DC/DC converter with hi
gh
galvanic isolation （4 kV） ensures that the user is
protected from the high voltage （secondary side）.
The power supplies for the driver may be the same a
s
used in the control board （0/+15V） without the
requirement of isolation. All information that is t
ransmitted
between input and output uses ferrite transformers,
resulting in high dv/dt immunity （75kV/
μ
s）.
The driver input stage is connected directly to the
control
board output and due to different control board ope
rating
voltages the SKHI10’s input circuit includes a user
voltage
level selector （+15V or +5V）.
In the following only the designation SKHI 10 is us
ed.
This is valid for both driver versions. If somethin
g is to be
explained special to SKHI 10/17 it will be descripe
d by
marking SKHI 10/17.
A. Features and Configuration of the Driver
A short description is given below. For detailed
information, please refer to section B.
a） The SKHI10 has an INPUT LEVEL SELECTOR circuit
which is adusted by J1 for two different levels. It
is
present for CMOS （15V） level, but can be changed by
the user to HCMOS （5V） level by solder bridging the
pads marked J1 together. For long input cables, we
do
not recommend the 5V level due to possible
disturbances emitted by the power side.
b） The ERROR MEMORY blocks the transmission of all
turn-on signals to the IGBT if either a short circu
it or
malfunction of V
S
is detected, and sends a signal to
the external control board through an open collecto
r
transistor.
c） With a FERRITE TRANSFORMER the information
between primary and secondary may flow in both
directions and high levels of dv/dt and isolation a
re
obtained.
d） A high frequency DC/DC CONVERTER avoids the
requirement of external isolated power supplies to
obtain the necessary gate voltage. An isolated ferr
ite
transformer in half-bridge configuration supplies t
he
necessary power to the gate of the IGBT. With this
feature, we can use the same power supply used in
the external control circuit, even if we are using
more
than one SKHI10, e.g. in H-bridge configurations.
e） Short circuit protection is provided by measuring
the
collector-emitter voltage with a V
CE
MONITORING
circuit. An additional circuit detects the short ci
rcuit
after a delay （determined by R
CE
,C
CE
） and decreases
the turn off speed （adjusted by R
goff
-SC） of the IGBT.
SOFT TURN-OFF under fault conditions is necessary
as it reduces the voltage overshoot and allows for
a
faster turn off during normal operation.
f） The OUTPUT BUFFER is responsible for providing th
e
correct current to the gate of the IGBT. If these s
ignals
do not have sufficient power, the IGBT will not swi
tch
properly, and additional losses or even the destruc
tion
of the IGBT may occur. According to the application
（switching frequency and gate charge of the IGBT） t
he
equivalent value of R
gon
and the R
goff
must be matched
to the optimum value. This can be done by putting
additional parallel resistors R
gon
, R
goff
with those
already on the board. If only one IGBT is to be use
d,
（instead of parallel connection） only one cable cou
ld
be connected between driver and gate by soldering
the two J2 areas together.
Fig.1 shows a simplified block diagram of the SKHI1
0
driver. Some preliminary remarks will help the
understanding:
• Regulated +15V must be present between pins 8,9 （V
s
）
and 10,11 （
⊥
）; an input signal （ON or OFF command to
the IGBTs） from the control system is supplied to p
in 2
（V
in
） where HIGH=ON and LOW=OFF.
• Pin 5 （V
CE
） at secondary side is normally connected to
the collector of the IGBT to monitor V
CE
, but for initial
tests without connecting the IGBT it must be connec
ted
to pin 1 （E） to avoid ERROR signal and enable the
output signals to be measured.
• The RESET input must be connected to 0V to enable
the V
in
signal. If it is left opened, the driver will be
blocked.
• To monitor the error signal, a pull-up resistor mu
st be
provided between pin 3 （ERROR） and V
S
.
B. Description of the Circuit Block Diagram
（Fig. 1）
The circuit in Fig. 1 shows the input on the left a
nd output
on the right （primary/secondary）.
1. Input level circuit
This circuit was designed to accept two different l
ogic
voltage levels. The standard level is +15V （factory
adjusted） intended for noisy environments or when l
ong
connections （l > 50 cm） between the external contro
l
circuit and SKHI10 are used, where noise immunity m
ust
be considerate. For lower power, and short connecti
ons
between control and driver, the TTL-HCMOS level （+
5V）
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